1. Technical Field of the Invention
The present invention relates to the correction of clock skew in a data transmissions system.
2. Background of the Invention
As the complexity of integrated circuits (ICs) increases, the speed at which they process information also increases. The speeds at which contemporary systems process data have increased such that a single chip may contain billions of transistors. Synchronized by a single system clock, billion-transistor ICs are often clocked at speeds greater than 2 Gigahertz (GHz). At these speeds, the timing signals for data transmission and data processing have such minute periods that they are easily disrupted or distorted. Variations in temperature, electromagnetic interference from neighbouring transmission lines, and even the minute resistance offered by transmission lines can introduce skew in the timing of data transmissions.
One method for reducing the effects of clock skew while efficiently utilizing the space on an IC is the serial transmission of parallel data between elements on a board. By converting parallel data into a single bit-by-bit sequential stream that travels from chip to chip, the possibility for skew is reduced by decreasing the number of physical channels which connect the source to its destination. Reducing a plurality of transmission lines to a single line eliminates the need to synchronize several datapaths, any one of which may be skewed. Due to the small amount of space allocated for each transmission line, interference or “crosstalk” between lines can occur in parallel transmission; a single transmission line is comparatively isolated and insulated, minimizing the opportunities for interference. Serial transmission is also more efficient in terms of space, as fewer pins are required on the chip to receive or send data. These differences do not only admit less skew in data transmission: the relative resistance of serial data transmission to the effects of clock skew also means that serial data transmissions may be clocked at higher frequencies than parallel data transmissions, as the user can have more confidence that serial data transmissions will not become as skewed as parallel data transmissions. The conversion of parallel data into a serial transmission requires the use of a Serializer/Deserializer (SerDes), which consists of a pair of logic blocks on either side of the transmission system, with one logic block on the transmit side to convert the parallel data into serial data, and another logic block at the receive side to convert the serial data back to parallel data.
Paradoxically, because serial data can be transmitted faster due to its relative resistance to the causes of skew, systems adapted for these higher data rates are more sensitive to variations in timing. Thus it is necessary to introduce additional means on the IC to discover and eliminate any skew that may have occurred in transmission. Employing a phase-locked loop (PLL) or a delay-locked loop (DLL) in the clock path of a circuit are common and effective methods for correcting clock drift. These circuits operate by comparing the input (or reference) signal with a second signal, and using the difference in phase or delay between those two signals to produce a third output signal which is fed back into the input of the circuit and is to be compared with the reference signal. If the difference between the output signal and the input signal drifts too far, the resultant differential signal pushes the frequency in whichever direction is required to correct the error, thereby eliminating skew.
While PLLs and DLLs are effective devices for correcting skew among data signals, they do not necessarily make efficient use of available chip space. Both PLLs and DLLs require a plurality of elements to be installed on an IC in order to function. An analog PLL requires a phase comparator, a low-pass filter, a voltage-controlled oscillator, and a clock divider; digital PLLs replace the oscillator with an additional clock and a counter to perform the same function. DLLs include an array of multiplexers to manipulate the delay of the output clock signal. On ICs where space is already at a premium, it is necessary to find a more space-efficient method of deskewing data signals.
Methods for sampling incoming data signals and deskewing said data signals without resorting to PLLs or DLLs are known in the prior art, but none of the prior art utilises a physical delay line controlled by a state machine to induce pre-existing chip architecture to create samples of an incoming data signal for the purposes of describing the data valid window of the incoming data signal and adjusting the clock signal of said incoming data signal to an optimum position within said data valid window.